VHDL

For the first time in my university life that i can actually tell myself that i might actually do well for a test, though minus the part that others might do well too. I did my VHDL test today, which is a programming test for digital design. It started off badly because i mixed up certain coding style with MATLAB, as i was using MATLAB a few days ago for my EE2012 experiment report. Luckily for me, after some trials and errors, i managed to get the styling right and continued to finish my program. It meets all requirement and i think it should be correct, so hopefully the result from this test can make up for the terrible result from my last test.